Cmac and Its Extensions for Efficient System Modelling and Diagnosis

This paper deals with the family of CMAC neural networks. The most important properties of this family are the extremely fast learning capability and the special architecture that lets effective digital hardware implementation possible. The paper gives an overview of the classical binary CMAC, shows the limitations of its modelling capability, gives a critical survey of its different extensions and suggests two further modifications. The aim of these modifications is to improve the modelling capability while maintain the possibility of effective realization. The basic element of the first suggested hardware structure is a new matrix vector multiplier which is based on canonical signed digit (CSD) number representation and distributed arithmetic. In the second version a hierarchical network structure and special sequential training method are proposed which may be a solution to the tradeoff between approximation error and generalization. The proposed versions among them a dynamic extension of the originally static CMAC are suitable for embedded applications where low cost and relatively high speed operation are the most important requirements.